Scaling of metal gate with aluminum containing metal layer for threshold voltage shift

ABSTRACT

A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

BACKGROUND

The present disclosure relates generally to semiconductor devices, andmore particularly to threshold voltage modifications in semiconductordevices.

P-type field effect transistors (pFET) formed on silicon containingsubstrates typically employ a gate structure including a boron (or otheracceptor) doped p-type polysilicon layer as a gate electrode depositedon top of a silicon dioxide or silicon oxynitride gate oxide layer. Thegate voltage is applied through this polysilicon layer to create aninversion channel in the n-type silicon underneath the gate oxide layer.For a pFET to work properly, the inversion should begin occurring atslightly negative voltages applied to the polysilicon (poly-Si) gateelectrode. This occurs as a consequence of the band alignment for thegate stack structure. For example, a poly-Si/gate oxide/n-type siliconstack forms a capacitor that swings into inversion at around 0 V. Thethreshold voltage Vt, which can be interpreted as the voltage at whichthe inversion starts occurring, is therefore approximately 0 V. Theexact value of the threshold voltages has some dependence on the dopinglevel in the silicon substrate, and can be varied somewhat by choosingan appropriate substrate doping level. When p-type field effecttransistors are fabricated using a dielectric, such as hafnium oxide orhafnium silicate, the flatband voltage of the device is shifted from itsideal position of close to about +1 V, to about 0+/−300 mV.

SUMMARY

A method of forming a p-type semiconductor device is provided, which inone embodiment employs an aluminum containing threshold voltage shiftlayer to produce a threshold voltage shift towards the valence band ofthe p-type semiconductor device. The method of forming the p-typesemiconductor device may include forming a gate structure on asubstrate, in which the gate structure includes a gate dielectric layerpositioned on the substrate, and an aluminum containing thresholdvoltage shift layer positioned on the gate dielectric layer. Ametal-containing layer may also be present on the aluminum containingthreshold voltage shift layer. The metal containing layer may be a metalnitride layer or a metal gate conductor. A p-type source region and ap-type drain region (hereinafter “p-type source and drain region”) maybe formed in the substrate adjacent to the portion of the substrate onwhich the gate structure is present.

In another embodiment, a p-type semiconductor device may be provided bya method that includes forming a gate dielectric layer positioned on asubstrate, in which the gate dielectric layer includes an aluminumcontaining threshold voltage shift layer embedded therein. Forming ametal containing layer positioned on the gate dielectric layer. A gatestructure is then formed from the gate dielectric layer, the aluminumcontaining threshold voltage shift layer and the metal containing layer,wherein the gate structure is present on a first portion of thesubstrate. P-type source and drain regions may be formed in thesubstrate adjacent to the first portion of the substrate on which thegate structure is present.

In a further embodiment, a p-type semiconductor device may be providedby a method that includes forming an aluminum containing thresholdvoltage shift layer on a substrate; forming a gate dielectric layer onthe aluminum containing threshold voltage shift layer; forming a metalcontaining layer in contact with the gate dielectric layer; and forminga gate structure from the aluminum containing threshold voltage shiftlayer, the gate dielectric layer and the metal containing layer, whereinthe gate structure is present on a first portion of the substrate.P-type source and drain regions are then formed in the substrateadjacent to the first portion of the substrate.

In another aspect of the invention, a p-type semiconductor device isprovided, in which an aluminum containing threshold voltage shift layerthat is present in the gate structure of the device induces a thresholdvoltage shift towards the valence band of the p-type semiconductordevice. In one embodiment, the p-type semiconductor structure includes agate structure present on a first portion of a silicon containingsubstrate, in which the gate structure includes a gate dielectric layerpresent on the silicon containing substrate, an aluminum containingthreshold voltage shift layer present on the gate dielectric layer and ametal nitride layer present on the aluminum containing threshold voltageshift layer. P-type source and drain regions may be present in a portionof the silicon containing substrate that is adjacent to the firstportion of the silicon containing substrate on which the gate structureis present, wherein the p-type semiconductor device has a thresholdvoltage ranging from −0.35 V to −0.1 V.

DESCRIPTION OF THE DRAWINGS

The following detailed description, given by way of example and notintended to limit the invention solely thereto, will best be appreciatedin conjunction with the accompanying drawings, wherein like referencenumerals denote like elements and parts, in which:

FIG. 1 is a side cross-sectional view depicting forming a gate structureon a substrate, in which the gate structure includes a gate dielectriclayer present on the substrate, an aluminum containing threshold voltageshift layer on the gate dielectric layer, and a metal nitride layerpresent on the aluminum containing threshold voltage shift layer, inaccordance with one embodiment of the present invention.

FIG. 2 is a side cross-sectional view depicting implanting dopants intothe substrate to provide p-type source and drain regions, in accordancewith one embodiment of the present invention.

FIG. 3 is a side cross-sectional view depicting forming silicidecontacts to the polysilicon gate conductor, the source region and thedrain region of a semiconductor device in which the gate stack of thesemiconductor device includes in order from top to bottom a gate stackcomposed of a polysilicon gate conductor, a metal nitride layer,aluminum containing threshold voltage shift layer, and a gate dielectriclayer, in accordance with one embodiment of the present invention.

FIG. 4 is a side cross-sectional view of another embodiment of asemiconductor device in accordance with the present invention, in whichthe gate stack of the semiconductor device includes in order from top tobottom a metal gate conductor, an aluminum containing threshold voltageshift layer, and a gate dielectric layer.

FIG. 5 is a side cross-sectional view of another embodiment of asemiconductor device in accordance with the present invention, in whichthe gate stack of the semiconductor device includes in order from top tobottom a polysilicon gate conductor, a metal nitride layer, a gatedielectric layer and an aluminum containing threshold voltage shiftlayer.

FIG. 6 is a side cross-sectional view of another embodiment of asemiconductor device in accordance with the present invention, in whichthe gate stack of the semiconductor device includes in order from top tobottom a metal gate conductor, a gate dielectric layer and an aluminumcontaining threshold voltage shift layer.

FIG. 7 is a side cross-sectional view of another embodiment of asemiconductor device in accordance with the present invention, in whichthe gate stack of the semiconductor device includes in order from top tobottom a polysilicon gate conductor, a metal nitride layer, and a gatedielectric layer, in which an aluminum containing threshold voltageshift layer is embedded in the gate dielectric layer.

FIG. 8 is a side cross-sectional view of another embodiment of asemiconductor device in accordance with the present invention, in whichthe gate structure of the semiconductor device includes from top tobottom a metal gate conductor, and a gate dielectric layer having analuminum containing threshold voltage shift layer embedded therein, inaccordance with the present invention.

FIG. 9 is a plot of threshold voltage (V) as a function of thedeposition period for a p-type semiconductor device having a gatestructure including an aluminum containing threshold voltage shiftlayer, in accordance with some embodiments of the present invention.

FIG. 10 is a plot of inversion thickness (Tinv) as a function of thedeposition period for the aluminum containing threshold voltage shiftlayer, in accordance with some embodiments of the present invention.

FIG. 11 is a plot of carrier mobility as a function of the depositionperiod for a p-type semiconductor device having a gate structureincluding an aluminum containing threshold voltage shift layer, inaccordance with some embodiments of the present invention.

DETAILED DESCRIPTION

Detailed embodiments of the present invention are disclosed herein;however, it is to be understood that the disclosed embodiments aremerely illustrative of the invention that may be embodied in variousforms. In addition, each of the examples given in connection with thevarious embodiments of the invention is intended to be illustrative, andnot restrictive. Further, the figures are not necessarily to scale, somefeatures may be exaggerated to show details of particular components.Therefore, specific structural and functional details disclosed hereinare not to be interpreted as limiting, but merely as a representativebasis for teaching one skilled in the art to variously employ thepresent invention.

In one embodiment, the present invention provides a method of forming ap-type semiconductor device that positions an aluminum containingthreshold voltage shift layer in a gate structure, wherein the aluminumcontaining threshold voltage shift layer effectuates a threshold voltageshift towards the valence band of the p-type semiconductor device. Whendescribing the inventive methods and structures, the following termshave the following meanings, unless otherwise indicated.

A “gate structure” means a structure used to control output current(i.e., flow of carriers in the channel) of a semiconducting device, suchas a field effect transistor (FET), and includes at least one gateconductor and at least one gate dielectric layer.

The “channel” is the portion of the substrate underlying the gatestructure and between the source and drain dopant regions.

As used herein, a “gate dielectric” is a layer of an insulator betweenthe semiconductor device substrate and the gate conductor.

A “gate conductor” means a conductive structure of the gate structure onthe gate dielectric.

As used herein, the terms “insulating” and “dielectric” denote amaterial having a room temperature conductivity of less than 10⁻¹⁰(Ω-m)⁻¹.

A “high-k” dielectric is a dielectric or insulating material having adielectric constant that is greater than the dielectric constant ofsilicon oxide (SiO₂).

As used herein, “threshold voltage” is the lowest attainable gatevoltage that will turn on a semiconductor device, e.g., transistor, bymaking the channel of the device conductive.

The term “inversion thickness” is a value extracted from valid inversioncapacitance-voltage (C-V) measurement for the gate structure of asemiconductor device. Its derivation is described as:

${T_{inv} = \frac{ɛ_{0} \cdot ɛ_{{SiO}\; 2}}{C_{\max}}},$

where ∈₀ is vacuum permittivity, ∈_(SiO2) is SiO₂ dielectric constant,and C_(max) is the maximum inversion capacitance from the abovementioned C-V measurement.

“Threshold voltage shift” as used herein means a shift in the Fermienergy of a p-type semiconductor device towards a valence band ofsilicon in the silicon containing substrate of the p-type semiconductordevice.

A “valence band” is the highest range of electron energies whereelectrons are normally present at absolute zero.

The term “direct physical contact” means that a first element, such as afirst structure, and a second element, such as a second structure, areconnected without any intermediary conducting, insulating orsemiconductor layers at the interface of the two elements.

The terms “overlying”, “atop”, “positioned on” or “positioned atop” meanthat a first element, such as a first structure, is present on a secondelement, such as a second structure, wherein intervening elements, suchas an interface structure may be present between the first element andthe second element.

References in the specification to “one embodiment”, “an embodiment”,“an example embodiment”, etc., indicate that the embodiment describedmay include a particular feature, structure, or characteristic, butevery embodiment may not necessarily include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to affect such feature, structure, or characteristicin connection with other embodiments whether or not explicitlydescribed.

For purposes of the description hereinafter, the terms “upper”, “lower”,“right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, andderivatives thereof shall relate to the invention, as it is oriented inthe drawing figures.

FIGS. 1-3 illustrate some of the basic processing steps that may beemployed in one embodiment of a method of forming a p-type semiconductordevice that positions an aluminum containing threshold voltage shiftlayer 14 in the gate structure 15 of the device. The aluminum containingthreshold voltage shift layer 14 that is present in the gate structure15 may produce a threshold voltage shift in the p-type semiconductordevice. The threshold voltage shift is typically towards the valenceband of the p-type semiconductor device. As used herein, “p-type” refersto the addition of trivalent impurities to an intrinsic semiconductorthat creates deficiencies of valence electrons. In one example, theaddition of boron, aluminum, or gallium to a type IV semiconductor, suchas Si, creates deficiencies of valence electrons.

FIG. 1 depicts one embodiment of forming a gate structure 15 on asubstrate 5, in which the gate structure 15 includes a gate dielectriclayer 13 present on the substrate 5, an aluminum containing thresholdvoltage shift layer 14 present on the gate dielectric layer 13, and ametal nitride layer 16 present on the aluminum containing thresholdvoltage shift layer 14. The substrate 5 may include, but is not limitedto, silicon containing materials, GaAs, InAs and other likesemiconductors. Silicon containing materials as used to provide thesubstrate 5 include, but are not limited to, Si, bulk Si, single crystalSi, polycrystalline Si, SiGe, amorphous Si, silicon-on-insulatorsubstrates (SOI), SiGe-on-insulator (SGOI),strained-silicon-on-insulator, annealed poly Si, and poly Si linestructures. In one embodiment in which the substrate 5 is asilicon-on-insulator (SOI) or SiGe-on-insulator (SGOI) substrate, thesilicon containing layer 4 (also referred to as SOI layer) that is atopthe buried insulating layer 3 can have a thickness greater than 10 nm.The buried insulating layer 3 may be composed of an oxide, such assilicon oxide, and may have a thickness ranging from 10 nm to 100 nm.The thickness of the silicon containing layer 2 that is underlying theburied insulating layer 3 may range from 10 nm to 500 nm. The SOI orSGOI substrate may be fabricated using a thermal bonding process, or maybe fabricated by an ion implantation process.

The substrate 5 may further include trench isolation regions 6. Thetrench isolation regions 6 can be formed by etching a trench in thesilicon containing layer 4 utilizing a dry etching process, such asreactive-ion etching (RIE) or plasma etching. The trenches mayoptionally be lined with a liner material, e.g., an oxide, and then CVDor another like deposition process is used to fill the trench with oxidegrown from tetraethylorthosilicate (TEOS) precursors, high-density oxideor another like trench dielectric material. After trench dielectricfill, the structure may be subjected to a planarization process.

Still referring to FIG. 1, the gate structure 15 may be formed atop thesubstrate 5 utilizing deposition, lithography and etching processes.More specifically, in one embodiment, a gate structure 15 may beprovided atop the substrate 5 by blanket depositing the layers of a gatestack, and then patterning and etching the gate stack to provide thegate structure 15. For example, forming the gate stack may includeblanket deposition of material layers including the gate dielectriclayer 13, the aluminum threshold voltage shift layer 14, and the metalnitride layer 16. In one example, the gate stack further includes aconductive semiconductor layer 17 present on the metal nitride layer 16.

The gate stack may be patterned using photolithography and etching toproduce the gate structure 15. In one example, following the depositionof the gate dielectric layer 13, the aluminum containing thresholdvoltage shift layer 14, the metal nitride layer 16, and the conductivesemiconductor layer 17 (when present), an etch mask may be formed atopthe uppermost layer of the gate stack, e.g., the metal nitride layer 16or conductive semiconductor layer 17 (when present). The etch masktypically protects the portion of the layered stack that provides thegate structure 15, wherein the portions exposed by the etch mask areremoved by an anisotropic etch process, such as a reactive ion etch.Reactive ion etch is a form of plasma etching, in which the surface tobe etched is placed on the RF powered electrode and takes on a potentialthat accelerates an etching species, which is extracted from a plasma,towards the surface to be etched, wherein a chemical etching reactiontakes place in the direction normal to the surface being etched. In oneembodiment, the etch mask may be provided by a patterned photoresistlayer.

The gate dielectric layer 13 of the gate structure 15 may be composed ofan oxide material. Suitable examples of oxides that can be employed asthe gate dielectric layer 13 include, but are not limited to: SiO₂,Al₂O₃, ZrO₂, HfO₂, Ta₂O₃, perovskite-type oxides and combinations andmulti-layers thereof. The gate dielectric layer 13 may be composed of ahigh k dielectric having a dielectric constant of greater than about4.0, and in some embodiments greater than 7.0. The high k dielectric mayinclude, but is not limited to, an oxide, nitride, oxynitride and/orsilicate including metal silicates and nitrided metal silicates. In oneembodiment, the high-k dielectric is comprised of an oxide such as, forexample, HfO₂, ZrO₂, Al₂O₃, TiO₂, La₂O₃, SrTiO₃, LaAlO₃, Y₂O₃ andmixtures thereof. Other examples of high k dielectrics suitable for useas the gate dielectric layer 13 in the present method include hafniumsilicate and hafnium silicon oxynitride.

The gate dielectric layer 13 can be formed by a thermal growth processsuch as, for example, oxidation, nitridation or oxynitridation. The gatedielectric layer 13 can also be formed by a deposition process such as,for example, chemical vapor deposition (CVD), plasma-assisted CVD,metal-organic chemical vapor deposition (MOCVD), atomic layer deposition(ALD), evaporation, reactive sputtering, chemical solution depositionand other like deposition processes. The gate dielectric layer 13 mayalso be formed utilizing any combination of the above processes. Thegate dielectric layer 13 typically has a thickness ranging from 1 nm to10 nm. In one example, the gate dielectric layer 13 has a thicknessranging from 2 nm to 5 nm. In one embodiment, the gate dielectric layer13 is in direct physical contact with a surface, e.g., upper surface, ofthe substrate 5.

The aluminum containing threshold voltage shift layer 14 of the gatestructure 15 may be composed of an aluminum containing conductivematerial, which may be substantially pure aluminum. In one embodiment,by “substantially pure” aluminum it is meant that the aluminum contentof the aluminum containing threshold voltage shift layer 14 is greaterthan 99.0%. In some embodiments, the aluminum content of the aluminumcontaining threshold voltage shift layer 14 may be greater than 99.5%.The aluminum containing threshold voltage shift layer 14 may have athickness of less than 10 Å. In one embodiment, the aluminum containingthreshold voltage shift layer 14 ranges from 1 Å to 5 Å. In anotherembodiment, the aluminum containing threshold voltage shift layer rangesfrom 2 Å to 3 Å. In another embodiment, the aluminum containingthreshold voltage shift layer 14 has a thickness of less than 2 Å. Inone example, the aluminum containing threshold voltage shift layer 14that is composed of substantially pure aluminum is in direct physicalcontact with a surface, e.g., upper surface, of the gate dielectriclayer 13.

The aluminum containing threshold voltage shift layer 14 may depositedby a physical vapor deposition (PVD) method, such as sputtering. As usedherein, “sputtering” means a method of depositing a film of metallicmaterial, in which a target of the desired material, i.e., source, isbombarded with particles, e.g., ions, which knock atoms from the target,and the dislodged target material deposits on the deposition surface.Examples of sputtering apparatus that may be suitable for depositing thealuminum containing threshold voltage shift layer 14 include DC diodetype systems, radio frequency (RF) sputtering, magnetron sputtering, andionized metal plasma (IMP) sputtering.

In one embodiment, a sputtering deposition process for depositing thealuminum containing threshold voltage shift layer 14 includes applyinghigh energy particles to strike a solid slab of high-purity aluminumtarget material, in which the high energy particles physically dislodgeatoms of the aluminum to be deposited on the gate dielectric layer 13.In one example, the ion energies of the high-energy particles, e.g.,positive ions from an argon gas flow discharge, range from 500 eV to5,000 eV. In another embodiment, the ion energies of the high-energyparticles range from 1,500 eV to 4,500 eV. In one embodiment, byhigh-purity aluminum it is meant that the aluminum content of the targetmaterial is greater than 99.0%. In some embodiments, the aluminumcontent of the target material may be as great as 99.95% with aremainder of incidental impurities. “Incidental impurities” denote anycontamination of the target, i.e., aluminum. Allowable ranges ofimpurities are less than 0.05 wt % for each impurity constituent and0.15 wt % for total impurity content. The sputtered aluminum atoms fromthe aluminum target may migrate through a vacuum and deposit on thedeposition surface, e.g., the gate dielectric layer 13. In one example,iron (Fe), copper (Cu), and silver (Ag) may be present in less than 5parts per million (ppm). In another example, uranium (U), thorium (Th)and other radioactive elements may be present in less than 100 parts perbillion (ppb).

Although physical vapor deposition (PVD) techniques have been describedabove for forming the aluminum containing threshold voltage shift layer14, chemical vapor deposition (CVD) and atomic layer deposition (ALD)have also been contemplated as a suitable deposition methods for formingthe aluminum containing threshold voltage shift layer 14.

In another embodiment, the aluminum containing threshold voltage shiftlayer 14 may be composed of titanium aluminum nitride (TiAlN). In oneexample, the titanium content of the titanium aluminum nitride may rangefrom 20 wt % to 80 wt %, the aluminum content of the titanium aluminumnitride may range from 20 wt % to 60 wt %, and the nitrogen content ofthe titanium aluminum nitride may range from 20 wt % to 60 wt %. Inanother example, the titanium content of the titanium aluminum nitridemay range from 30 wt % to 60 wt %, the aluminum content of the titaniumaluminum nitride may range from 25 wt % to 40 wt %, and the nitrogencontent of the titanium aluminum nitride may range from 25 wt % to 50 wt%.

The titanium aluminum nitride may be deposited using physical vapordeposition (PVD), such as sputtering. In one embodiment, a sputteringdeposition process for depositing titanium aluminum nitride (TiAlN)includes applying high energy particles to strike a solid slab of atitanium aluminum alloy target material, in which the high energyparticles physically dislodge atoms of titanium and aluminum to bedeposited on the gate dielectric layer 13. In another embodiment, thesputtering apparatus may include dual targets, e.g., a first targetcomposed of titanium and a second target composed of aluminum. Thesputtered atoms of titanium and aluminum typically migrate through avacuum and deposit on the deposition surface, e.g., the gate dielectriclayer 13. In one example, the ion energies of the high-energy particles,e.g., positive ions from an argon gas flow discharge range from 500 eVto 5,000 eV. In another embodiment, the ion energies of the high-energyparticles range from 1,500 eV to 4,500 eV.

The source of nitrogen for the titanium aluminum nitride (TiAlN) may beprovided by nitrogen gas (N₂). The nitrogen source may be introduced tothe sputtering chamber as the sputtered atoms of titanium and aluminumare migrating towards the deposition surface, e.g., the gate dielectriclayer 13. In one example, the nitrogen source is provided byco-sputtering from a titanium (Ti) and an aluminum (Al) target in anAr/N₂ gas mixture. In one example, the aluminum containing thresholdvoltage shift layer 14 composed of titanium aluminum nitride may be indirect physical contact with a surface, e.g., upper surface, of the gatedielectric layer 13.

The metal nitride layer 16 that is present on the aluminum containingthreshold voltage shift layer 14 may be composed of TiN, TaN, WN or acombination thereof. It is noted that the metal nitride layer 16 may becomposed of other metal materials, so long as the metal nitride layer 16does not include aluminum. In one embodiment, the metal nitride layer 16may have a thickness ranging from 25 Å to 200 Å. In another embodiment,the metal nitride layer 16 has a thickness ranging from 50 Å to 100 Å.

The metal nitride layer 16 may be deposited using physical vapordeposition (PVD), such as sputtering. In one embodiment, the sputteringdeposition process for forming the metal nitride layer 16 includesapplying high-energy particles to strike a solid slab of a metal targetmaterial to provide the metal constituent of the metal nitride layer 16,such as titanium. The high-energy particles physically dislodge metalatoms of target material, which are then deposited on the aluminumcontaining threshold voltage shift layer 14.

The source of nitrogen for the metal nitride layer 16 may be provided bynitrogen gas (N₂). The nitrogen source may be introduced to thesputtering chamber as the sputtered atoms of the metal constituent ofthe metal nitride layer 16 are migrating towards the deposition surface,e.g., the aluminum containing threshold voltage shift layer 14.

In one example, the metal nitride layer 16 is composed of titaniumnitride (TiN), in which the titanium concentration ranges from 30% to70%. In another example, the titanium concentration of the titaniumnitride (TiN) metal nitride layer 16 ranges from 45% to 55%.

In the embodiments of the invention in which a conductive semiconductorlayer 17 is present on the metal nitride layer 16, the conductivesemiconductor layer 17 may be composed of single crystal Si, SiGe, SiGeCor combinations thereof. In another embodiment, the conductivesemiconductor layer 17 may further comprise a metal and/or silicide. Inother embodiments, the conductive semiconductor layer 17 is comprised ofmulti-layered combinations of the aforementioned conductive materials.In one example, the conductive semiconductor layer 17 is composed of asingle layer of polysilicon. The conductive semiconductor layer 17 maybe formed by chemical vapor deposition (CVD) or physical vapordeposition (PVD). In one embodiment, the conductive semiconductor layer17 may be doped to a p-type conductivity. For example, the conductivesemiconductor layer 17 may be doped with an element from group IIIA ofthe periodic table of elements, such as boron, with an ion implantationdose ranging from 1E15 cm⁻² to about 5E16 cm².

Variations of CVD processes suitable for forming the conductivesemiconductor layer 17 include, but are not limited to, AtmosphericPressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD(EPCVD), Metal-Organic CVD (MOCVD) and combinations thereof. Theconductive semiconductor layer 17 has a thickness ranging from 1 nm to20 nm. In one example, the conductive semiconductor layer 17 has athickness ranging from 5 nm to 10 nm. In one embodiment, the conductivesemiconductor layer 17 is in direct physical contact with a surface,e.g., upper surface, of the metal nitride layer 16.

FIG. 2 depicts implanting dopants into the substrate 5 to provide p-typesource and drain region. P-type source and drain extension regions 37may be formed using an ion implantation process. More specifically, inone example, when forming p-type source and drain extension regions 37the dopant species may be boron or BF₂. Boron may be implanted utilizingimplant energies ranging 0.2 keV to 3.0 keV with an implant dose rangingfrom 5×10¹⁴ atoms/cm² to 5×10¹⁵ atoms/cm². BF₂ may be implantedutilizing implant energies ranging from 1.0 keV to 15.0 keV and havingan implant dose ranging from 5×10¹⁴ atoms/cm² to 5×10¹⁵ atoms/cm².

Following the p-type source and drain extension regions 37 implantation,the structure may be annealed to promote diffusion of the dopantspecies. The p-type source and drain extension regions 37 may beactivated by an annealing process, such as rapid thermal anneal. In oneexample, the rapid thermal annealing temperature is carried out using atemperature ranging from 750° C. to 1200° C. for a time period rangingfrom 1.0 second to 20.0 seconds. The anneal process may be conductedfollowing the completion of all of the implant processing steps toreduce the thermal budget of the manufacturing process.

Still referring to FIG. 2, a spacer 42 may be formed in direct physicalcontact with the sidewalls of the gate structure 15. The spacer 42 maybe composed of oxide, i.e., SiO₂, but may also comprise nitride oroxynitride materials. Each spacer 42 may have a width ranging from 50.0nm to 100.0 nm. The spacer 42 can be formed by deposition and etchprocesses. For example, a conformal dielectric layer may be depositedusing deposition processes, including, but not limited to, chemicalvapor deposition (CVD), plasma-assisted CVD, and low-pressure chemicalvapor deposition (LPCVD). Following deposition, the conformal dielectriclayer is then etched to define the geometry of the spacer 42 using ananisotropic plasma etch procedure such as, reactive ion etch.

P-type deep source and drain regions 38 may be implanted into thesubstrate 5. Typical implant species for the p-type deep source anddrain regions 38 may include boron or BF₂. The p-type deep source/draindiffusion region 38 can be implanted with boron utilizing an energyranging from 1.0 keV to 8.0 keV with a dose ranging from 1×10¹⁵atoms/cm² to 7×10¹⁵ atoms/cm². The p-type deep source and draindiffusion region 38 may also be implanted with BF₂ with an implantenergy ranging from 5.0 keV to 40.0 keV and a dose ranging from 1×10¹⁵atoms/cm² to 7×10¹⁵ atoms/cm².

Following p-type deep source and drain regions 38 implantation, thestructure may be annealed to promote diffusion of the dopant species. Inone embodiment, the anneal process step may be conducted following thecompletion of all of the implant processing steps to reduce the thermalbudget of the manufacturing process. In one embodiment, the p-typesource and drain regions may be present in an n-type well region (notshown) of the substrate 5.

FIG. 3 depicts one embodiment of forming silicide contacts 50 to thegate structure 15 and the source and drain regions, i.e., the p-typesource and drain extension regions 37 and p-type deep source and draindiffusion regions 38. Silicide formation typically requires depositing arefractory metal, such as Ni, Co, or Ti, onto the surface of aSi-containing material. Following deposition, the structure is thensubjected to an annealing step using thermal processes, such as rapidthermal annealing. During thermal annealing, the deposited metal reactswith Si forming a metal semiconductor alloy, e.g., silicide.

In one embodiment, a conformal layer of a dielectric material 51 may beblanket deposited atop the entire substrate to provide an etch stoplayer. The conformal layer of the dielectric material 51 may be composedof a dielectric material, including but not limited to, oxide, nitridesand oxynitrides. An interlevel dielectric 52 may be deposited atop theconformal dielectric material 51. The interlevel dielectric 52 may beselected from the group consisting of silicon containing materials suchas SiO₂, Si₃N₄, SiO_(x)N_(y), SiC, SiCO, SiCOH, and SiCH compounds; theabove-mentioned silicon containing materials with some or all of the Sireplaced by Ge; carbon-doped oxides; inorganic oxides; inorganicpolymers; hybrid polymers; organic polymers such as polyamides or SiLK™;other carbon-containing materials; organo-inorganic materials such asspin-on glasses and silsesquioxane-based materials; and diamond-likecarbon (DLC, also known as amorphous hydrogenated carbon, α-C:H).Additional choices for the interlevel dielectric 52 include: any of theaforementioned materials in porous form, or in a form that changesduring processing to or from being porous and/or permeable to beingnon-porous and/or non-permeable.

The interlevel dielectric layer 52 may be formed by various deposition,including, but not limited to, spinning from solution, spraying fromsolution, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD),sputter deposition, reactive sputter deposition, ion-beam deposition,and evaporation. The conformal layer of a dielectric material 51 and theinterlevel dielectric layer 52 are then patterned and etched to form viaholes to the various source and drain and gate conductor regions of thesubstrate 5. Following via formation, interconnects 53 are formed bydepositing a conductive metal into the via holes using depositionprocessing, such as CVD or plating. The conductive metal may include,but is not limited to, tungsten, copper, aluminum, silver, gold, andalloys thereof.

The above described method provides a p-type semiconductor device thatpositions an aluminum containing threshold voltage shift layer 14 withina gate structure 15, wherein the aluminum containing threshold voltageshift layer 14 effectuates a threshold voltage shift towards the valenceband of the p-type semiconductor device. In one embodiment, thresholdvoltage shift provided by the aluminum containing threshold voltageshift layer 14 may be as great as 0.3 V towards the valence band of thep-type semiconductor device. It is noted that the above method may beincorporated into a replacement gate process, in which a dummy gate ispresent during the formation of the doped regions and the annealing ofthe device, wherein the dummy gate may then be replaced with afunctional gate including the aluminum containing threshold voltageshift layer 14.

Referring to FIG. 3, in one embodiment, the present method may provide ap-type semiconductor device including a gate structure 15 present on afirst portion 70 of a silicon containing substrate 5, in which the gatestructure 15 includes at least a gate dielectric layer 13 on the siliconcontaining substrate 5, an aluminum containing threshold voltage shiftlayer 14 on the gate dielectric layer 13 and a metal nitride layer 16 onthe aluminum containing threshold voltage shift layer 14. P-type sourceand drain regions, i.e., the p-type source and drain extension regions37 and p-type deep source and drain diffusion regions 38, may be presentin a second portion of the silicon containing substrate 5 that isadjacent to the first portion 70 of the silicon containing substrate 5on which the gate structure 15 is present. The p-type semiconductordevice may have a threshold voltage ranging from −0.35 V to −0.1 V. Inone embodiment, the p-type semiconductor device has a threshold voltageranging from −0.3 V to −0.1 V. In an even further embodiment, the p-typesemiconductor device has a threshold voltage ranging from −0.25 V to−0.15 V.

The p-type semiconductor device may have an inversion thickness (Tinv)ranging from 13.5 Å to 15 Å. In another embodiment, the inversionthickness of the p-type semiconductor device ranges from 10 Å to 20 Å.In an even further embodiment, the inversion thickness of the p-typesemiconductor device ranges from 11 Å to 20 Å. The p-type semiconductordevice may have a mobility of charge carriers ranging from 80cm²/(v·sec) to 120 cm²/(v·sec). In one embodiment, the p-typesemiconductor device may have a mobility of charge carriers ranging from80 cm²/(v·sec) to 120 cm²/(v·sec).

Although not depicted in FIG. 3, a second metal nitride layer may bepresent between the aluminum containing threshold voltage shift layer 14and the gate dielectric layer 13. In one embodiment, the second metalnitride layer may have a thickness ranging from 25 Å to 200 Å. Inanother embodiment, the second metal nitride layer has a thicknessranging from 50 Å to 100 Å. The second metal nitride layer may becomposed of titanium nitride (TiN), in which the titanium concentrationranges from 30% to 70%. In another example, the titanium concentrationof the titanium nitride (TiN) ranges from 45% to 55%.

FIGS. 4-8 depict other structural embodiments of the present inventionthat include an aluminum containing threshold voltage shift layer 14.FIG. 4 depicts a gate structure 15 including from top to bottom a metalgate conductor 18, an aluminum containing threshold voltage shift layer14, and a gate dielectric layer 13, e.g., high-k gate dielectric, thatis present on a surface of a semiconductor substrate 5. In theembodiment depicted in FIG. 4, a metal gate conductor 18 is substitutedfor the conductive semiconductor layer 17 that is composed ofpolysilicon. The metal gate conductor 18 may be composed of a metalnitride, such as titanium nitride (TiN) or tantalum nitride (TaN).Alternatively, the metal gate conductor 18 may be a metal selected fromthe group consisting of tantalum (Ta), titanium (Ti), tungsten (W) orCopper (Cu). In a further embodiment, the metal gate conductor 18 may becomposed of a metal silicide, i.e., metal semiconductor alloy. Similarto the embodiment, depicted in FIG. 3, the aluminum containing thresholdvoltage shift layer 14 may be composed of substantially pure aluminum(Al) or titanium aluminum nitride (TiAlN). It is noted that theremaining elements that are depicted in FIG. 4 have been described abovein FIGS. 1-3.

FIG. 5 depicts another embodiment of a p-type semiconductor device, inwhich the gate structure 15 of the p-type semiconductor device includesin order from top to bottom, a conductive semiconductor layer 17 that iscomposed of polysilicon, a metal nitride layer 16, a gate dielectric 13and an aluminum containing threshold voltage shift layer 14 that ispresent on the surface of the semiconductor substrate 5. It is notedthat a silicide contact 50 may be present on the conductivesemiconductor layer 17. The silicide contact 50 may be composed of anymetal semiconductor alloy. The gate dielectric 13 may be composed of ahigh-k dielectric. Similar to the embodiment, depicted in FIG. 3, thealuminum containing threshold voltage shift layer 14 may be composed ofsubstantially pure aluminum (Al) or titanium aluminum nitride (TiAlN).It is noted that the remaining elements that are depicted in FIG. 4 havebeen described above in FIGS. 1-3.

FIG. 6 is a side cross-sectional view of another embodiment of a p-typesemiconductor device, in which the gate structure 15 of the p-typesemiconductor device includes in order from top to bottom a metal gateconductor 18, a gate dielectric layer 13 and an aluminum containingthreshold voltage shift layer 14 that is present on the surface of thesemiconductor substrate 5. It is noted that a silicide contact 50 may bepresent on the conductive semiconductor layer 17. The silicide contact50 may be composed of any metal semiconductor alloy. In the embodimentdepicted in FIG. 6, a metal gate conductor 18 is substituted for theconductive semiconductor layer 17 that is composed of polysilicon thatis depicted in FIG. 5. The metal gate conductor 18 may be composed of ametal nitride, such as titanium nitride (TiN) or tantalum nitride (TaN).Alternatively, the metal gate conductor 18 may be a metal selected fromthe group consisting of tantalum (Ta), titanium (Ti), tungsten (W) andCopper (Cu). The gate dielectric layer 13 may be composed of a high-kdielectric. Similar to the embodiment depicted in FIG. 3, the aluminumcontaining threshold voltage shift layer 14 may be composed ofsubstantially pure aluminum (Al) or titanium aluminum nitride (TiAlN).It is noted that the remaining elements that are depicted in FIG. 4 havebeen described above in FIGS. 1-3.

FIG. 7 depicts another embodiment of a p-type semiconductor device inaccordance with the present invention. In the embodiment depicted inFIG. 7, the gate stack of the p-type semiconductor device includes inorder from top to bottom a conductive semiconductor layer 17 that iscomposed of polysilicon, a metal nitride layer 16, and a gate dielectriclayer 13, in which an aluminum containing threshold voltage shift layer14 is embedded in the gate dielectric layer 13. By embedded it is meantthat the aluminum containing threshold voltage shift layer 14 is presentwithin the gate dielectric layer 13 so that a lower portion of the gatedielectric layer 13 is present below the aluminum containing thresholdvoltage shift layer 14, and an upper portion of the gate dielectriclayer 13 is present above the aluminum containing threshold voltageshift layer. The gate dielectric layer 13 may be composed of a high-kdielectric. The aluminum containing threshold voltage shift layer 14 maybe composed of substantially pure aluminum (Al) or titanium aluminumnitride (TiAlN). It is noted that the remaining elements that aredepicted in FIG. 4 have been described above in FIGS. 1-3.

FIG. 8 depicts another embodiment of a p-type semiconductor device inaccordance with the present invention, in which the gate structure 15 ofthe p-type semiconductor device includes a metal gate conductor 18, anda gate dielectric layer 13 having an aluminum containing thresholdvoltage shift layer 14 embedded therein. In the embodiment depicted inFIG. 8, a metal gate conductor 18 is substituted for the conductivesemiconductor layer 17 that is composed of polysilicon that is depictedin FIG. 7. The metal gate conductor 18 may be composed of a metalnitride, such as titanium nitride (TiN) or tantalum nitride (TaN).Alternatively, the metal gate conductor 18 may be a metal selected fromthe group consisting of tantalum (Ta), titanium (Ti), tungsten (W) andcopper (Cu). In an even further embodiment, the metal gate conductor maybe 18 may be composed of a metal semiconductor alloy, i.e., silicide.The gate dielectric 13 may be composed of a high-k dielectric. Thealuminum containing threshold voltage shift layer 14 may be composed ofsubstantially pure aluminum (Al) or titanium aluminum nitride (TiAlN).It is noted that the remaining elements that are depicted in FIG. 4 havebeen described above in FIGS. 1-3.

Although some embodiments of the invention have been described generallyabove, the following examples are provided to further illustrate thepresent invention and demonstrate some advantages that arise therefrom.It is not intended that the invention be limited to the specificexamples disclosed.

EXAMPLES

Test samples of p-type semiconductor devices (10 micron (width)×10micron (length)), i.e., field effect transistors, were producedincorporating an aluminum containing threshold voltage shift layerwithin the gate structure of the p-type semiconductor device. Table 1includes the composition of the aluminum containing threshold voltageshift layer. Specifically, Table 1 illustrates the composition of theinitial aluminum containing material (aluminum deposition composition)being deposited atop the gate dielectric layer, and the time period fordeposition of the aluminum containing material. Samples 2-8 included aninitial aluminum containing material being deposited by sputtering froma high purity aluminum target. The time period for sputtering of thealuminum containing material from the high purity aluminum target rangedfrom 2-24 seconds, which typically equated to a substantially purealuminum layer having a thickness of less than 5 Å. Sample 1 is atitanium nitride deposited layer having no aluminum present therein.Samples 9-14 included an initial aluminum containing material composedof titanium aluminum nitride (TiAlN) being deposited by sputtering froma TiAl target, in which the nitrogen was introduced by N₂ gas. Each ofthe samples included a metal nitride layer composed of titanium nitridedeposited overlying the aluminum containing threshold voltage shiftlayer by sputtering.

TABLE 1 aluminum aluminum deposition deposition SAMPLE # compositiontime (sec) metal nitride/oxidation 1 Aluminum (Al) 0 Titanium nitride(TiN) 2 Aluminum (Al) 2 Titanium nitride (TiN) 3 Aluminum (Al) 4Titanium nitride (TiN) 4 Aluminum (Al) 8 Titanium nitride (TiN) 5Aluminum (Al) 12 Titanium nitride (TiN) 6 Aluminum (Al) 16 Titaniumnitride (TiN) 7 Aluminum (Al) 20 Titanium nitride (TiN) 8 Aluminum (Al)24 Titanium nitride (TiN) 9 Titanium Aluminum 2 Titanium nitride (TiN)Nitride (TiAlN) 10 Titanium Aluminum 4 Titanium nitride (TiN) Nitride(TiAlN) 11 Titanium Aluminum 8 Titanium nitride (TiN) Nitride (TiAlN) 12Titanium Aluminum 12 Titanium nitride (TiN) Nitride (TiAlN) 13 TitaniumAluminum 16 Titanium nitride (TiN) Nitride (TiAlN) 14 Titanium Aluminum20 Titanium nitride (TiN) Nitride (TiAlN)

FIG. 9 is a plot of measurements of the threshold voltage (V) of samples1-14 included in Table 1 as a function of the aluminum deposition periodof the aluminum containing threshold voltage shift layer. FIG. 9illustrates that the aluminum containing threshold voltage shift layerprovides a shift in threshold voltage from −0.4 V, as measured from ap-type semiconductor device that does not include the aluminumcontaining threshold voltage shift layer, to −0.1 V, in which the shiftin threshold voltage increases with increasing aluminum deposition time.

FIG. 10 is a plot of inversion thickness (Tinv) (inversion C-V measuredat 1 MHz frequency) of samples 1-14 included in Table 1 as a function ofthe deposition period for the aluminum containing threshold voltageshift layer. FIG. 10 illustrates through samples 1-14 that the inversionthickness (Tinv) of the p-type semiconductor devices decreases withinincreasing aluminum content, i.e., increasing aluminum deposition time,of the aluminum containing threshold voltage shift layer on the gatedielectric. The thinner the inversion thickness (Tinv), the higher thedrive current of the p-type semiconductor device. The thicker theinversion thickness (Tinv), the lower the drive current of the p-typesemiconductor device. FIG. 10 illustrates that the inversion thickness(Tinv) decreases with increasing aluminum content of the aluminumcontaining threshold voltage shift layer, which results in a higherdrive current in the p-type semiconductor device including the aluminumcontaining threshold voltage shift layer.

FIG. 11 is a plot of carrier mobility (μ) for samples 1-14 that areincluded in Table 1. FIG. 11 depicts normalized data. The carriermobility was measured as a function of the deposition period for thealuminum containing threshold voltage shift layer. FIG. 11 illustratesthat peak mobility in p-type semiconductor devices is provided byaluminum containing threshold voltage shift layers with an initialaluminum containing material sputtered from a high purity aluminumtarget for deposition times ranging from 8 to 12 seconds. The depositiontime ranging from 8 to 12 seconds correlates to a thickness of thealuminum containing threshold voltage shift layer that ranges from 2 Åto 5 Å.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1. A method of forming a p-type semiconductor device comprising: forminga gate dielectric layer positioned on a substrate; forming an aluminumcontaining threshold voltage shift layer positioned on the gatedielectric layer; forming a metal containing layer positioned on thealuminum containing threshold voltage shift layer; forming a gatestructure from the gate dielectric layer, the aluminum containingthreshold voltage shift layer and the metal containing layer, whereinthe gate structure is present on a first portion of the substrate; andforming p-type source and drain regions in the substrate adjacent to thefirst portion of the substrate.
 2. The method of claim 1, wherein thealuminum containing threshold voltage shift layer is composed of asubstantially pure layer of aluminum that is formed using physical vapordeposition.
 3. The method of claim 1, wherein the physical vapordeposition includes sputtering from an aluminum target composed of 99.9%aluminum.
 4. The method of claim 1, wherein the aluminum containingthreshold voltage shift layer is composed of TiAlN.
 5. The method ofclaim 1, wherein the metal containing layer is a first metal nitridelayer that is substantially free of aluminum.
 6. The method of claim 5,wherein the first metal nitride layer is composed of TiN, TaN, WN or acombination thereof.
 7. The method of claim 5, wherein the first metalnitride layer is TiN deposited using sputtering, in which titanium ofthe first metal nitride layer is provided by a solid Ti target and thenitride of the metal nitride layer is provided by a nitrogen containinggas.
 8. The method of claim 5, wherein the aluminum containing thresholdvoltage shift layer is in direct physical contact with an upper surfaceof the gate dielectric layer, and the first metal nitride layer is indirect physical contact with the aluminum containing threshold voltageshift layer.
 9. The method of claim 5, wherein the gate dielectric layeris present on an upper surface of the substrate, a second metal nitridelayer is present on the upper surface of the gate dielectric layer, thealuminum containing threshold voltage shift layer is present on an uppersurface of the second metal nitride layer, and the first metal nitridelayer is present on an upper surface of the aluminum containingthreshold voltage shift layer.
 10. The method of claim 1, wherein thegate structure further comprises a semiconductor containing layer thatis present on the metal nitride layer.
 11. The method of claim 1,wherein the aluminum containing threshold voltage shift layer produces athreshold voltage shift as great as 300 mV towards the valence band ofthe p-type semiconductor device.
 12. A method of forming a p-typesemiconductor device comprising: forming a gate dielectric layerpositioned on a substrate, in which the gate dielectric layer includesan aluminum containing threshold voltage shift layer embedded therein;forming a metal containing layer positioned on the gate dielectriclayer; forming a gate structure from the gate dielectric layer, thealuminum containing threshold voltage shift layer and the metalcontaining layer, wherein the gate structure is present on a firstportion of the substrate; and forming p-type source and drain regions inthe substrate adjacent to the first portion of the substrate.
 13. Themethod of claim 12, wherein the gate structure further comprises asemiconductor containing layer that is present on the metal nitridelayer.
 14. A method of forming a p-type semiconductor device comprising:forming an aluminum containing threshold voltage shift layer on asubstrate; forming a gate dielectric layer on the aluminum containingthreshold voltage shift layer; forming a metal containing layer incontact with the gate dielectric layer; forming a gate structure fromthe aluminum containing threshold voltage shift layer, the gatedielectric layer and the metal containing layer, wherein the gatestructure is present on a first portion of the substrate; and formingp-type source and drain regions in the substrate adjacent to the firstportion of the substrate.
 15. A p-type semiconductor device comprises: agate structure present on a first portion of a silicon containingsubstrate, the gate structure comprising a gate conductor, a gatedielectric layer and an aluminum containing threshold voltage shiftlayer, wherein the aluminum containing threshold voltage shift layer ispresent in contact with the gate dielectric; and p-type source and drainregions present in a portion of the silicon containing substrate that isadjacent to the first portion of the silicon containing substrate onwhich the gate structure is present, wherein the p-type semiconductordevice has a threshold voltage ranging from −0.35 V to −0.1 V.
 16. Thep-type semiconductor device of claim 15, wherein the semiconductordevice has an inversion thickness (Tinv) ranging from 13.5 Å to 15 Å.17. The p-type semiconductor device of claim 15, wherein the gatedielectric layer is present on an upper surface of the siliconcontaining substrate, and the aluminum containing threshold voltageshift layer is present on or embedded within the gate dielectric layer.18. The p-type semiconductor device of claim 15, wherein the aluminumcontaining threshold voltage shift layer is present on an upper surfaceof the silicon containing substrate and the gate dielectric layer ispresent on an upper surface of the aluminum containing threshold voltageshift layer.
 19. The p-type semiconductor device of claim 15, furthercomprising at least one of a first metal containing layer present on anupper surface of the aluminum containing threshold voltage shift layer,and a second metal containing layer present between the aluminumcontaining threshold voltage shift layer.
 20. The p-type semiconductordevice of claim 15, wherein the gate dielectric layer comprises SiO₂,Al₂O₃, ZrO₂, HfO₂, Ta₂O₃, TiO₂, perovskite-type oxides or combinationsand multi-layers thereof.
 21. The p-type semiconductor device of claim15 further comprising a gate conductor comprised of a metal,semiconductor or metal semiconductor alloy present overlying the gatedielectric layer.